1. Field of the Invention
The present invention relates to a CMOS circuit for averaging digital-to-analog converters which is used as a sub-circuit for pulse-density digital-to-analog conversion or pulse-density analog-to-digital conversion.
2. Description of the Related Art
In its simplest form, an averaging circuit contains a shift register which is supplied with the pulse-density-modulated signal and whose output signals are combined as current or voltage signals via a summing circuit. The sum output provides the desired averaged signal, which is generally applied as a current signal to a capacitor. Instead of the term "pulse-density modulation," the term "signal-delta modulation" is frequently used.
If both phases of the signals are taken from the individual shift-register cells, the in-phase and out-of-phase components are summed and then the difference of the two sums is formed. The difference represents the desired averaged signal, but not without the constant DC component (See FIG. 1).
Because of the high clock rates of the pulse-density modulated signals, the following circuit or signal characteristics interfere with the averaging:
variations in the instants at which the individual signals change state, which variations may be caused by circuit unbalances, phase jitter, or the data history; and
amplitude variations of the individual signals caused by, for example, signal noise or spurious signals.
The effects of circuit unbalances, which may result, for example, in varying leading and trailing edges, and the effects of the data history are prevented by means of gate circuits associated with the shift-register cells. The gate circuits cut a shorter gating interval out of each data interval, so that the averaging is performed with this temporally shortened signal. Each logic 1, irrespective of the data history, represents a separate pulse which starts from the logic 0 level. Thus, asymmetries in the leading and trailing edges can no longer have a disturbing effect, and since each signal begins with a logic 0, the data history is of no consequence, too. Unfortunately, this method, also referred to as "gating," increases the sensitivity to phase jitter, since the phase variations have a greater effect than the shortened gating interval.
According to European Application EP-A-0 335 988 (corresponding to U.S. patent application Ser. No. 321,593), the disadvantageous effects of phase jitter on the gating intervals can be avoided by effecting the gating in both the master phase and the slave phase of the shift clock. To accomplish this, the signals from the Q outputs of all gates are summed and so are the signals from the Q' outputs (see FIG. 2). By the inclusion of the master and slave phases in the gating, the phase variations of the gate clock are compensated for. For instance, if the gating interval in the master phase is too long, the gating interval in the slave phase is automatically correspondingly shorter, as shown, for example, in FIG. 3. Clock sensitivity is an essential prerequisite for high-resolution converters.
The EP-A-0 335 988 application further describes how the amplitudes of the individual signals can be made more uniform by using a separate signal source for each signal. The logic states of the master and slave cells and the gate signal control only the signal path in the respective gate circuit for the separate signal source. Each gate circuit contains two electronic switches in series. The first electronic switch connects the signal source to the neutral gate output outside the gating interval or to the input of the second electronic switch during the gating interval. The first electronic switch is controlled via a clock-dependent control input to which the gate signal is applied. The second electronic switch is controlled via a data-dependent control input which is connected to the Q (true) and Q' (complement) outputs of the associated master or slave cell. The two output terminals of the second electronic switch form the Q and Q' terminals of the gate circuit.
Since currents are easy to switch and sum, all signal sources are implemented with separate constant-current sources which are all connected to a common bias source. All Q' terminals of the gate circuits are coupled to a common first bus which is connected to the input of a current mirror serving as a current-difference stage. Similarly, all Q terminals of the gate circuits are coupled to a common second bus which is connected to the output of the current mirror and from whose node the differential current can be taken. All neutral gate terminals are combined via a gate bus which is connected to a neutral current sink.
The gate clock is synchronous with the shift clock but differs in phase from the latter by a certain amount for reliable data transfer. Thus, (1) all slave cells are connected to either the current-difference stage or the neutral current sink while all master cells are connected to the neutral current sink, or (2) all master cells are connected to either the current-difference stage or the neutral current sink while all slave cells are connected to the neutral current sink.
The current difference is formed in the EP-A-0 335 988 application by means of a pnp-transistor current mirror whose input and output are connected to the Q bus and the Q' bus, respectively. From the Q' bus, the differential current can be taken as an averaging signal, as shown, for example, in FIG. 2.
It is not readily possible to convert this prior art circuit arrangement, which is implemented in bipolar technology, to CMOS technology, particularly for high clock rates. And this applies even though MOS transistors, in contrast to bipolar transistors, have an ideal current ratio, because no base current has to be taken out of the transmitted current. The main disadvantage of MOS transistors is their square-law current characteristic EQU I.sub.DS -.beta.(U.sub.GS -U.sub.T).sup.2
and their relatively large gate-source capacitance. This has an extremely disadvantageous effect in MOS currents mirrors if high-frequency current have to be mirrored. In that case, part of the input current is used to reverse the charge of the gate-source capacitances of the current-mirror transistors. Since the gate-source voltage is proportional to the root of the drain current, and the gate current is proportional to the change in gate-source voltage, the drain current of the output transistor of the current mirror is distorted, the distribution increasing with increasing frequency. In the case of pulse-density-modulated signals with their high clock frequencies, these distortions fall into the useful-signal band through signal mixing.